Typical ultra large scale integration (ULSI) and very large scale integration (VLSI) semiconductor chips include arrays of electrical devices having contacts interconnected by patterns of metal strips. The patterns of metal strips in these chips are often multi-layered and separated by layers of an insulating material. During fabrication, it is desirable to produce substantially planar surfaces in forming these layers.
Planar device layers are necessary to facilitate masking and etching procedures. A planar surface provides a critical constant depth of focus across the device for exposing patterns during photolithographic operations to produce sharply focused features in the corresponding layer patterns. In addition, planar surfaces contribute to the formation of device layers having constant thicknesses across a semiconductor wafer. The constant thicknesses of the layers improve the yield of dies cut from the wafer and the reliability of such dies.
Nevertheless, fabrication of planar device surfaces including those having recessed or damascene structures, such as interconnect strips, has presented complications with conventional etch back techniques. Presently, plasma etching or reactive ion etching (RIE) of metals with a resist planarizing medium are used for planarization in fabricating recessed structures. A description of an exemplary RIE process is provided in R. Kraft and S. Prengle, "High-Density Plasma Etching 0.35 Micron Polysilicon Gates", Solid State Technology, pp. 57-60 (August, 1995), which is incorporated by reference herein. However, these techniques tend to suffer from increasingly poor yield as device geometries increasingly become smaller than 0.5 .mu.m.
Another planarization technique is chemical mechanical polishing (CMP). CMP is typically performed by polishing a semiconductor wafer on a rotating platen using a slurry typically composed of fumed silica or alumina suspended in an aqueous-based solution. Exemplary CMP methods are described in R. Jairath et al., "Chemical Mechanical Polishing: Process Manufacturability", Solid State Technology, pp. 71-77 (July, 1994), which is incorporated by reference herein. However, such a polishing process for global planarization of dielectric materials, such as silicon dioxide, or soft metals, such as aluminum and copper, tend to cause "dishing". "Dishing" refers to the excessive removal of material in one or more regions during planarization causing the surface in such regions to be lower relative to surrounding surface regions. In particular, application of a CMP process to structures recessed in a substrate tends to cause dishing of the recessed structure relative to the surrounding substrate surface rather than planarization.
The degree of dishing that occurs during such polishing is strongly topographic feature size dependent. Wide depressed regions in a surface tend to polish faster than narrow depressed regions. As a consequence, wide depressed regions typically experience a higher degree of dishing than narrow depressed regions. Exemplary wide recessed structures include power buses which often have widths greater than 200 .mu.m on the same device layer as signal interconnect strips having widths less than 0.5 .mu.m.
Hard mask materials, such as silicon nitride, that polish at a slower rate than the material of the recessed structures have been deposited over the recessed structures in order to reduce the amount of dishing. Exemplary planarization methods that employ hard masks are described in U.S. Pat. No. 5,362,669, which is incorporated by reference herein. However, such use of hard masks reduces but does not necessarily eliminate dishing. Moreover, the hard mask must polish at a much lower rate during the CMP process than the recessed structure material. Accordingly, the processing time required for such planarization is often much longer than that required by other conventional planarization techniques. As a consequence, this technique tends to significantly increase the overall device fabrication time which is undesirable in the commercial production of large quantities of the devices.
Thus, planarization techniques that limit dishing and device fabrication times is desirable.